资 源 简 介
The AD55321 is a 32-channel， 14-bit voltage-output DAC with an addiTIonal infinite sample-and-hold mode. The selected DAC register is written to via the 3-wire serial interface; VOUT for this DAC is then updated to reflect the new contents of the DAC register. DAC selecTIon is accomplished via Address Bits A0–A4. The output voltage range is determined by the offset voltage at the OFFS_IN pin and the gain of the output amplifier. It is restricted to a range from VSS + 2 V to VDD – 2 V because of the headroom of the output amplifier. The device is operated with AVCC = 5 V ± 5%; DVCC = 2.7 V to 5.25 V; VSS = −4.75 V to −16.5 V; and VDD = 8 V to 16.5 V. The AD5532 requires a stable 3 V reference on REF_IN as well as an offset voltage on OFFS_IN.
