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Synthesizable 266 MBits/s DDR SDRAM Controller
The DDR, DCM, and SelectI/O™ features in the Virtex™-II architecture make it the perfectchoice for implementing a controller of a Double Data Rate (DDR) SDRAM. The Digital ClockManager (DCM) provides the required Delay Locked Loop (DLL), Digital Phase Shift (DPS),and Digital Frequency Synthesis (DFS) functions. This application note describes a controllerdesign for a 16-bit DDR SDRAM. The application note and reference design are enhancedversions of XAPP200 targeted to the Virtex-II series of FPGAs. At a clock rate of 133 MHz,16-bit data changes at both clock edges. The reference design is fully synthesizable andachieves 133 MHz performance with automatic place and route tools.
