首页| 行业标准| 论文文档| 电子资料| 图纸模型
购买积分 购买会员 激活码充值

您现在的位置是:团子下载站 > 其他 > AD9575,pdf daasheet(Network Cl

AD9575,pdf daasheet(Network Cl

  • 资源大小:212
  • 上传时间:2021-12-13
  • 下载次数:0次
  • 浏览次数:53次
  • 资源积分:1积分
  • 标      签: 时钟分配芯片 Network

资 源 简 介

The AD9575 provides a highly integrated, dual output clockgenerator funcTIon including an on-chip PLL core that isopTImized for network clocking. The integer-N PLL design isbased on the Analog Devices, Inc., proven portfolio of high performance, low jitter frequency synthesizers to maximize linecard performance. Other applicaTIons with demanding phasenoise and jitter requirements also benefit from this part.The PLL secTIon consists of a low noise phase frequency detector (PFD), a precision charge pump, a low phase noise voltagecontrolled oscillator (VCO), and pin selectable feedback and output dividers.
VIP VIP