资 源 简 介
Operates from a single 1.8 V analog power supply and features a separate digital output driver supply to accommodate 1.8 V CMOS or 1.8 V LVDS logic families. 2. The patented sample-and-hold circuit maintains excellent performance for input frequencies up to 200 MHz and is designed for low cost， low power， and ease of use. 3. Includes a standard serial port interface that supports various product features and funcTIons， such as data output formatTIng， internal clock divider， power-down， DCO/data TIming， and offset adjustments. 4. Packaged in a 64-lead， RoHS-compliant LFCSP that is pin compaTIble with the AD9650， AD9269， and AD9268 16-bit ADCs， the AD9258 and AD9648 14-bit ADCs， the AD9628 and AD9231 12-bit ADCs， and the AD9204 10-bit ADC， enabling a simple migration path between 10-bit and 16-bit converters sampling from 20 MSPS to 125 MSPS.
