EISA System Architecture

80486 System ArchitectureAbout This BookThe MindShare Architecture Series..... 1OrganizaTIon of This Book..... 2Part One – The EISA SpecificaTIon .. 2EISA Overview ..... 2EISA Bus Structure Overview... 2EISA Bus ArbitraTIon.. 2Interrupt Handling..... 2Detailed DescripTIon of EISA Bus... 3ISA Bus Cycles  3EISA CPU and Bus Master Bus Cycles ... 3EISA DMA.... 3EISA System Configuration  3Part Two – The Intel 82350DT EISA Chipset  3EISA System Buses ..... 3Bridge, Translator, Pathfinder, Toolbox . 3Intel 82350DT EISA Chip Set .... 4Who This Book Is For. 4Prerequisite Knowledge... 4Documentation Conventions. 4Hex Notation. 5Binary Notation... 5Decimal Notation 5Signal Name Representation..... 5Bit Field Identification (logical bit or signal groups) .. 5We Want Your Feedback .. 6Bulletin Board 6Mailing Address . 6Part One – EISA SpecificationChapter 1: EISA OverviewIntroduction .. 9Compatibility With ISA... 10Memory Capacity 10Synchronous Data Transfer Protocol ... 10Enhanced DMA Functions..... 10Bus Master Capabilities ... 11Data Bus Steering ..... 12Bus Arbitration... 12Edge and Level-Sensitive Interrupt Requests... 12Automatic System Configuration.. 12EISA Feature/Benefit Summary..... 13Chapter 2: EISA Bus Structure OverviewCommunity of Processors. 15Limitations of ISA Bus Master Support 16EISA Bus Master Support . 17EISA System Bus Master Types..... 20Types of Slaves in EISA System.... 21Chapter 3: EISA Bus ArbitrationEISA Bus Arbitration Scheme.. 23Preemption... 28Example Arbitration Between Two Bus Masters.... 29Memory Refresh . 30Chapter 4: Interrupt HandlingISA Interrupt Handling Review .... 33ISA Interrupt Handling Shortcomings 34Phantom Interrupts ..... 34Limited Number of IRQ Lines .. 35EISA Interrupt Handling.. 35Shareable IRQ Lines .... 35Phantom Interrupt Elimination  40Chapter 5: Detailed Description of EISA BusIntroduction .. 41Address Bus Extension ..... 43Data Bus Extension... 45Bus Arbitration Signal Group.. 45Burst Handshake Signal Group..... 48Bus Cycle Definition Signal Group ..... 48Bus Cycle Timing Signal Group.... 49Lock Signal ... 49Slave Size Signal Group... 50AEN Signal ... 50Chapter 6: ISA Bus CyclesIntroduction .. 538-bit ISA Slave Device 5316-bit ISA Slave Device.... 54Transfers With 8-bit Devices . 54Transfers With 16-bit Devices .. 57Standard 16-bit Memory ISA bus Cycle . 58Standard 16-bit I/O ISA bus Cycle . 61Zero Wait State ISA bus Cycle Accessing 16-bit Device.... 64ISA DMA Bus Cycles. 67ISA DMA Introduction ..... 678237 DMAC Bus Cycle 68Chapter 7: EISA CPU and Bus Master Bus CyclesIntro to EISA CPU and Bus Master Bus Cycles. 71Standard EISA Bus Cycle. 72General ... 72Analysis of EISA Standard Bus Cycle... 73Performance Using EISA Standard Bus Cycle.... 75Compressed Bus Cycle 75General ... 75Performance Using Compressed Bus Cycle.. 76Burst Bus Cycle ... 77General ... 77Analysis of EISA Burst Transfer  77Performance Using Burst Transfers  82DRAM Memory Burst Transfers ..... 82Downshift Burst Bus Master ..... 82Chapter 8: EISA DMADMA Bus Cycle Types 83Introduction.. 83Compatible DMA Bus Cycle ..... 84Description ... 84Performance and Compatibility ..... 84Type A DMA Bus Cycle.... 85Description ... 85Performance and Compatibility ..... 85Type B DMA Bus Cycle .... 86Description ... 86Performance and Compatibility ..... 87Type C DMA Bus Cycle.... 87Description ... 87Performance and Compatibility ..... 87EISA DMA Transfer Rate Summary ..... 88Other DMA Enhancements.... 88Addressing Capability  88Preemption .... 89Buffer Chaining... 89Ring Buffers... 90Transfer Size.. 90Chapter 9: EISA System ConfigurationISA I/O Address Space Problem.... 91EISA Slot-Specific I/O Address Space. 94EISA Product Identifier.... 98EISA Configuration Registers.. 100Configuration Bits Defined by EISA Spec . 101EISA Configuration Process .. 101General ... 101Configuration File Naming . 102Configuration Procedure .. 103Configuration File Macro Language ..... 104Example Configuration File  104Example File Explanation. 110Part Two – Intel 82350DT EISA ChipsetChapter 10: EISA System BusesIntroduction .. 117Host Bus.. 118EISA/ISA Bus  119X-Bus .... 119Chapter 11: Bridge, Translator, Pathfinder, ToolboxBus Cycle Initiation.. 123Bridge... 124Translator ..... 128Address Translation.... 128Command Line Translation  128Pathfinder..... 129Toolbox 132Chapter 12: Intel 82350DT EISA ChipsetIntroduction .. 133EISA Bus Controller (EBC) and EISA Bus Buffers (EBBs).... 134General ... 134CPU Selection 135Data Buffer Control and EISA Bus Buffer (EBB)  137General... 137Transfer Between 32-bit EISA Bus Master and 8-bit ISA Slave 139Transfer Between 32-bit EISA Bus Master and 16-bit ISA Slave.... 145Transfer Between 32-bit EISA Bus Master and 16-bit EISA Slave . 150Transfer Between 32-bit EISA Bus Master and 32-bit EISA Slave . 153Transfer Between 32-bit EISA Bus Master and 32-bit Host Slave.. 155Transfer Between 16-bit EISA Bus Master and 8-bit ISA Slave 156Transfer Between 16-bit EISA Bus Master and 16-bit ISA Slave.... 158Transfer Between 16-bit EISA Bus Master and 16-bit EISA Slave . 160Transfer Between 16-bit EISA Bus Master and 32-bit EISA Slave . 160Transfer Between 16-bit ISA Bus Master and 8-bit ISA Slave .. 162Transfer Between 16-bit ISA Bus Master and 16-bit ISA Slave  162Transfer Between 16-bit ISA Bus Master and 16-bit EISA Slave.... 163Transfer Between 16-bit ISA Bus Master and 32-bit EISA Slave.... 164Transfer Between 32-bit Host CPU and 32-bit Host Slave. 165Transfer Between 32-bit Host CPU and 8-bit ISA Slave... 165Transfer Between 32-bit Host CPU and 16-bit ISA Slave. 166Transfer Between 32-bit Host CPU and 16-bit EISA Slave  167Transfer Between 32-bit Host CPU and 32-bit EISA Slave  167Address Buffer Control and EBB..... 168Host CPU Bus Master  170EISA Bus Master ... 170ISA Bus Master ..... 170Refresh Bus Master..... 171DMA Bus Master .. 171Host Bus Interface Unit..... 172ISA Bus Interface Unit. 176EISA Bus Interface Unit .... 179Cache Support..... 180Reset Control . 181Slot-Specific I/O Support . 181Clock Generator Unit .. 181I/O Recovery. 182Testing.... 182ISP interface unit. 18382357 Integrated System Peripheral (ISP). 183Introduction.. 183NMI Logic..... 185Interrupt Controllers ... 185DMA Controllers  186System Timers ..... 187Central Arbitration Control. 188Refresh Logic. 188Miscellaneous Interface Signals  188Glossary.. 193Index..... 201