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74LS73A pdf datasheet

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  • 标      签: 74LS7

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DM54LS73A/DM74LS73A Dual NegaTIve-Edge-TriggeredMaster-Slave J-K Flip-Flops with Clearand Complementary OutputsGeneral DescripTIonThis device contains two independent negaTIve-edge-triggeredJ-K flip-flops with complementary outputs. The J andK data is processed by the flip-flops on the falling edge ofthe clock pulse. The clock triggering occurs at a voltagelevel and is not directly related to the transiTIon time of thenegative going edge of the clock pulse. The data on the Jand K inputs is allowed to change while the clock is high orlow without affecting the outputs as long as setup and holdtimes are not violated. A low logic level on the clear inputwill reset the outputs regardless of the levels of the otherinputs.

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