资 源 简 介
This 14-bit registered buffer is designed for 2.3-V to 3.6-V VCC operaTIon and SSTL_2 data input and output levels.
All inputs are compaTIble with the JEDEC Standard for SSTL_2, except the LVCMOS reset (RESET) input. All outputs are SSTL_2, Class II compaTIble.
When RESET is low, the differenTIal input receivers are disabled, and undriven (floating) data and clock inputs are allowed. In addition, when RESET is low, all registers are reset, and all outputs are forced low. The LVCMOS RESET input must always be held at a valid logic high or low level.
To ensure defined outputs from the register before a stable clock has been supplied, RESET must be held in the low state during power up.
The SN74SSTL16857 is characterized for operation from 0°C to 70°C.
