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UPSD HARDWARE DESCRIPTION . 8Figure 1. uPSD32xx Functional Modules . 8Special Function Registers (SFR) 9MCU Module Registers . . . 9PSD Module Registers . . . 9Figure 2. Memory Map and Address Space . . . . 9Table 1. SFR Memory Map . . . 10Table 2. PSD Module Register Address Offset 11MCU MODULE. . . . 13TIMERS/COUNTERS . 14Timer 0 and Timer 1 . . . . 14Mode 0. . . 14Figure 3. Timer/Counter Mode 0: 13-bit Counter 14Mode 1. . . 14Mode 2. . . 15Figure 4. Timer/Counter Mode 2: 8-bit Auto-reload . 15Mode 3. . . 15Figure 5. Timer/Counter Mode 3: Two 8-bit Counters. . 15Timer 2 . . 1616-bit Capture. . 16Figure 6. Timer 2 in Capture Mode 1616-bit Auto-reload . 17Figure 7. Timer 2 in Auto-Reload Mode . 17Baud Rate Generator . . . 17Special Function Registers for Use with the Timers. 18Table 3. Control Register for Timer0 and Timer1 (TCON) 18Table 4. Timer Mode Register for Timer0 and Timer1 (TMOD) . 18Table 5. Control Register for Timer2 (T2CON) 18INTERRUPT SYSTEM . 19Figure 8. Interrupt System . . . . 19Table 6. Special Function Registers for Use with the Interrupt System . 20Interrupt Priority . 20Table 7. Priority Levels and Vector Addresses 20Interrupt Enable Structure . . . 21Table 8. Description of the IE Bits 21Table 9. Description of the IEA Bits . . . . 21PULSE WIDTH MODULATION (PWM) 22Figure 9. Four-Channel, 8-bit PWM Block Diagram . 22How to Determine the Pulse-width-ratio of the PWM Output 23How to Determine the Repetition Frequency of the PWM Output . 23How to Determine the Polarity of the PWM Output. . 23How to Determine the Input Clock Frequency to the 8-bit counter of PWM4 . . . 23How to Determine the Period and Pulse Width of the PWM4 Output 23Figure 10.PWM4 With Programmable Pulse Width and Frequency . . 23How to Determine the Polarity of the PWM4 Output. 23Figure 11.Programmable PWM4 Channel Block Diagram 24Table 10. Special Function Registers for Use with the PWM . . . 25SUPERVISORY FUNCTION (LVD AND WATCHDOG) . 26Figure 12.RESET Configuration 26Watchdog Timer – SFR . 26Table 11. Description of the WDRST Bits 26Table 12. Description of the WDKEY Bits 26Figure 13.RESET Pulse Width . 27STANDARD SERIAL INTERFACE UART . . 28Table 13. Description of the SCON and SCON2 Bits 28Four Operation Modes . 29Mode 0. . . 29Figure 14.Serial Port Mode 0 Waveforms 29Mode 1. . . 29Figure 15.Serial Port Mode 1 Waveforms 29Mode 2. . . 30Figure 16.Serial Port Mode 2 Waveforms 30Mode 3. . . 30Figure 17.Serial Port Mode 3 Waveforms 30UART Baud Rates 31Using Timer 1 to Generate Baud Rates . 31Using Timer 2 to Generate Baud Rates . 31POWER-SAVING MODES . . 32Table 14. Changes of Activity on Entering a Power-Saving Mode 32Idle Mode 32Table 15. Power Control Register, PCON 32Power-down Mode 33I²C BUS INTERFACE . 34Figure 18.Block Diagram of the I2C Bus Serial I/O . . 34S1CON or S2CON, 35Table 16. Serial Control Register (S1CON, S2CON) 35Table 17. Description of the S1CON and S2CON Bits. . 35S1STA or S2STA, . 36Table 18. Serial Status Register (S1STA, S2STA) . . 36Table 19. Description of the S1STA and S2STA Bits 36S1DAT or S2DAT, . 36Table 20. Data Shift Register (S1DAT, S2DAT) 36S1ADR or S2ADR, 36Table 21. Address Register (S1ADR, S2ADR) . 36USB BUS. . . . 37Summary of the USB Standard . 37Figure 19.USB Bus Topology . . 37Figure 20.USB Bulk Transaction – 1 . . . . 38Table 22. USB Bulk Transaction 38Figure 21.USB Bulk Transaction – 2 . . . . 38Figure 22.USB Interrupt Transaction . . . . 39USB Low-speed Device . 40Figure 23.Device Termination – Full-speed . . . . 40Figure 24.Device Termination – Low-speed . . . 40Figure 25.USB Input/Output Design inside the uPSD32xxA . . . . 41Figure 26.Typical USB Connection Circuit for 5V (uPSD32xx) Systems . 41Special Control Registers . . . . 42Table 23. USB SFR Memory Map . 42Table 24. USB Address Register (UADR: 0EEh) 43Table 25. Description of the UADR Bits . . 43Table 26. USB Interrupt Enable Register (UIEN: 0E9h). 43Table 27. Description of the UIEN Bits . . 43Table 28. USB Interrupt Status Register (UISTA: 0E8h). 44Table 29. Description of the UISTA Bits . 44Table 30. USB Endpoint0 Transmit Control Register (UCON0: 0EAh) 45Table 31. Description of the UCON0 Bits 45Table 32. USB Endpoint1 (and 2) Transmit Control Register (UCON1: 0EBh) . 46Table 33. Description of the UCON1 Bits 46Table 34. USB Control Register (UCON2: 0ECh) 46Table 35. Description of the UCON2 Bits 46Table 36. USB Endpoint0 Status Register (USTA: 0EDh) . 47Table 37. Description of the USTA Bits . . 47Table 38. USB Endpoint0 Data Receive Register (UDR0: 0EFh) 47Table 39. USB Endpoint0 Data Transmit Register (UDT0: 0E7h) 47Table 40. USB Endpoint1 Data Transmit Register (UDT1: 0E6h) 47Table 41. USB Prescaler Register (USCL: 0E1h) 47DDC INTERFACE. . 48Figure 27.DDC Interface Block Diagram . 48Table 42. DDCCON Register (DDCCON) 49Table 43. Description of the DDCCON Register Bits . 49Table 44. SWNEB Bit Function . 50Figure 28.Transmit Mode Waveform . . . . 50Figure 29.Read Mode Sequence 51Figure 30.Transmission Protocol in the DDC1 Interface. 52ON-CHIP OSCILLATOR CIRCUIT . 53Figure 31.Pierce Oscillator . . . . 53Figure 32.Driving μPSD Clock from an Oscillator or an External Source 53ANALOG-TO-DIGITAL CONVERTOR (ADC) . . . . 54Figure 33.A/D Block Diagram . . 54ADC-Related Special Function Registers . . . 55Table 45. ADC Special Function Register, Memory Map55Table 46. Description of the ACON Bits . 55ADC Interrupts. 55I/O PORTS (MCU MODULE) . 56Table 47. I/O Port Functions . . . 56Table 48. P1SFS (91h) . . 56Table 49. P3SFS (93h) . . 56Table 50. P4SFS (94h) . . 56PSD MODULE.. . . . 57MEMORY BLOCKS.58Primary Flash Memory and Secondary Flash Memory 58Ready/Busy (PC3) . 58Flash Memory Sector Protect . . 58Table 51. Flash Protection Register . . . . 58Table 52. Secondary Flash Protection Register 58Table 53. Instructions . . . 59SRAM . . . 60Memory Addressing . . . 60Priority . . . 60Figure 34.Priority Level of Memory and I/O Components in the PSD Module . 60VM Register.. . . 60Table 54. VM Register . . . 60Figure 35.Combined Space Mode . 61Flexibility . 61Figure 36.Different Splits of Memory to Meet Application Demands . . 61Page Register. . 62Figure 37.Page Register Increases the Effective Core Space . . 62PLD BLOCKS 63Figure 38.PLD Diagram . . 63Table 55. DPLD and CPLD Inputs . 64Decode PLD (DPLD) . . . 65Figure 39.Decode PLD (DPLD) . 65Complex PLD (CPLD) . . 66Figure 40.Macrocell and I/O Port 66Output Macrocells (OMC) . . . . 67Figure 41.CPLD Output Macrocell . 67Product Term Allocator . 68Input Macrocells (IMC) . 68Figure 42.Input Macrocell 68I/O PORTS. . . 69Figure 43.General I/O Port Architecture . 69Port Operating Modes . . 70Table 56. Port Operating Modes 70Table 57. Port Operating Mode Settings . 70PLD I/O Mode. . 71Address Out Mode . 71Peripheral I/O Mode . . . . 71Figure 44.Peripheral I/O Mode . 71Port Configuration Registers (PCR) . . 72Table 58. Port Configuration Registers (PCR) . . 72Table 59. Port Pin Direction Control, Output Enable P.T. Defined 72Table 60. Drive Register Pin Assignment 72Port Data Registers . . . . 73Data In . . . 73Data Out Register . 73Output Macrocells (OMC) 73OMC Mask Register . . . . 73Input Macrocells (IMC) . . 73Enable Out.. . . . 73Table 61. Port Data Registers . . 73Ports A and B.. 74Figure 45.Port A and Port B Structure . . . 74Port C . . . 75Figure 46.Port C Structure 75Port D . . . 76Figure 47.Port D Structure 76POWER MANAGEMENT UNIT (PMU) 77Stand-by Mode.77Power-down Mode 77Figure 48.APD Unit 77Table 62. Power-down Mode’s Effect on Ports . 78Figure 49.Enable Power-down Flow Chart . . . . 79PSD Chip Select Input (CSI, PD2) . . . . 79Turbo Mode. . . 79PMMR Registers . 80Table 63. Power Management Mode Register PMMR0. 80Table 64. Power Management Mode Register PMMR2. 80RESET TIMING. . . . 81Figure 50.Reset (RESET) Timing . 81Table 65. Status During Power-on RESET, Warm RESET and Power-down Mode . . 81IN SYSTEM PROGRAMMING (ISP) 82Table 66. JTAG Enable Register 82Table 67. Pin Descriptions for FlashLINK/RLINK Adapter Assembly . 82IN-APPLICATION PROGRAMMING (IAP) . . 84Figure 51.Before IAP . . . . 84Figure 52.During IAP . . . . 84Figure 53.After IAP 84DEVELOPMENT TOOLS . . . 85Keil Software. . 85Figure 54.Keil Software uVision2 . 85NOHAU In-Circuit Emulator . . 86Figure 55.NOHAU In-Circuit Emulator . . . 86DK3200 Development Board from ST . 87Figure 56. 87FlashLINK/RLINK JTAG ISP Cable . . . . 88Figure 57.Pinout for FlashLINK/RLINK Adapter and Target System . . 88Figure 58.FlashLINK/RLINK Cable Assembly . . 89JTAG Gang Programmer . . . . 89Figure 59. 89REVISION HISTORY . . 89Table 68. Document Revision History . . . 89
