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CY74FCT823CT,pdf(9-Bit Bus-Int

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  • 标      签: Interface

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This bus-interface register is designed to eliminate the extra packages required to buffer exisTIng registers and provide extra data width for wider address/data paths or buses carrying parity. The CY74FCT823T is a 9-bit-wide buffered register with clock-enable (EN) and clear (CLR) inputs that are ideal for parity bus interfacing in high-performance microprogrammed systems. It is ideal for use as an output port requiring high IOL/IOH. This device is designed for high-capacitance load drive capability, while providing low-capacitance bus loading at both inputs and outputs. Outputs are designed for low-capacitance bus loading in the high-impedance state. This device is fully specified for parTIal-power-down applicaTIons using Ioff.
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