资 源 简 介
1.0 INTRODUCTION 11.1 PROM Programmer vsSystem-Processor ControlledProgramming 11.2 Information Download andUpload 1Version Updates (Download) 1Data Acquisition (Upload) 12.0 DEVICE FEATURES AND ISWAPPLICATIONCONSIDERATIONS 22.1 Flash Memory Pinouts 22.2 Command RegisterArchitecture 4Simplified Processor Interface 4Command Register Reset 5Data Protection on PowerTransitions 52.3 VPP Specifications 63.0 HARDWARE DESIGN FOR ISW 63.1 VPP Generation 63.1.1 Regulating Down fromHigher Voltage 63.1.2 Pumping 5V up to 12V 63.1.3 Absolute Data Protection ÐVPP On/Off Control 73.1.4 Writes and Reads duringVPP Transitions 73.1.5 Other VPP Considerations 73.1.6 VPP Circuitry and TraceLayout 83.2 Communications Ð Getting Datato and from the FlashMemory 8CONTENTS PAGE4.0 SOFTWARE DESIGN FOR ISW 84.1 System Integration Ð Boot CodeRequirements 84.1.1 ISW Flag Check 94.2 Communication Protocols andFlash Memory ISW 94.3 Data Accumulation SoftwareTechniques 104.4 Reprogramming Routines 104.4.1 Quick-Erase Algorithm 10Algorithm Timing Delays 10High Performance ParallelDevice Erasure 114.4.2 Quick-Pulse ProgrammingAlgorithm 12Algorithm Timing Delays 12High Performance ParallelDevice Programming 124.4.3 Pulse Width TimingTechniques 13Software Methods andExamples 13Hardware Methods 135.0 SYSTEM DESIGN EXAMPLE: AN80C186 DESIGN 146.0 SUMMARY 15
