资 源 简 介
The CDC3S04 is a four-channel low-power low-jittersine-wave clock buffer. It can be used to buffer a single master clock to mulTIple peripherals. The foursine-wave outputs （CLK1–CLK4） are designed forminimal channel-to-channel skew and ultralow addiTIve output jitter.
Each output has its own clock request inputs whichenables the dedicated clock output. These clockrequests are acTIve-high （can also be changed to be acTIve-low via I 2C）， and an output signal is generated that can be sent back to the master clock to request the clock （MCLK_REQ）。 MCKL_REQ is an open-source output and supports the wired-OR function（default mode）。 It needs an external pulldown resistorMCKL_REQ can be changed to wired-AND or push- pull functionality via I 2C
