资 源 简 介
The CY7C1345G is a 128K &TImes; 36 synchronous cache RAM designed to interface with high speed microprocessors with minimum glue logic. The maximum access delay from clock rise is 8.0 ns （100 MHz version）。 A 2-bit on-chip counter captures the first address in a burst and increments the address automaTIcally for the rest of the burst access. All synchronous inputs are gated by registers controlled by a posiTIve edge triggered Clock Input （CLK）。 The synchronous inputs include all addresses， all data inputs， address pipelining chip enable （CE1）， depth expansion chip enables （CE2 and CE3）， burst control inputs （ADSC， ADSP， and ADV）， write enables （BWx， and BWE）， and global write （GW）。 Asynchronous inputs include the output enable （OE） and the ZZ pin. The CY7C1345G enables either interleaved or linear burst sequences， selected by the MODE input pin. A HIGH selects an interleaved burst sequence， while a LOW selects a linear burst sequence. Burst accesses are iniTIated with the processor address strobe （ADSP） or the cache controller address strobe （ADSC） inputs. Addresses and chip enables are registered at rising edge of clock when either address strobe processor （ADSP） or address strobe controller （ADSC） is active. Subsequent burst addresses are internally generated as controlled by the Advance pin （ADV）。 The CY7C1345G operates from a +3.3 V core power supply while all outputs operate with either a +2.5 or +3.3 V supply. All inputs and outputs are JEDEC standard JESD8-5 compatible. For a complete list of related documentation， click here.
