资 源 简 介
The CY7C1461AV33/CY7C1463AV33 are 3.3 V， 1M &TImes; 36/2M &TImes; 18 Synchronous Flow-Through Burst SRAMs designed specifically to support unlimited true back-to-back read and write operaTIons without the inserTIon of wait states. The CY7C1461AV33/CY7C1463AV33 is equipped with the advanced NoBL logic required to enable consecutive read and write operations with data being transferred on every clock cycle. This feature dramatically improves the throughput of data through the SRAM， especially in systems that require frequent write-read transitions. All synchronous inputs pass through input registers controlled by the rising edge of the clock. The clock input is qualified by the Clock Enable （CEN） signal， which when deasserted suspends operation and extends the previous clock cycle. Maximum access delay from the clock rise is 6.5 ns （133 MHz device）。 Write operations are controlled by the two or four Byte Write Select （BWX） and a Write Enable （WE） input. All writes are conducted with on-chip synchronous self timed write circuitry. Three synchronous Chip Enables （CE1， CE2， CE3） and an asynchronous Output Enable （OE） provide for easy bank selection and output tri-state control. To avoid bus contention， the output drivers are synchronously tri-stated during the data portion of a write sequence. For a complete list of related documentation， click here.
