资 源 简 介
74F646, 74F646A Octal transceiver/register, non-inverTIng (3-State)74F648, 74F648AOctal transceiver/register, inverTIng (3-State)
The 74F646/74F646A and 74F648/74F648A transceivers/registersconsist of bus transceiver circuits with 3–state outputs, D–typeflip–flops, and control circuitry arranged for mulTIplexed transmissionof data directly from the input bus or the internal registers. Data onthe A or B bus will be clocked into the registers as the appropriateclock pin goes high. Output enable (OE) and DIR pins are providedto control the transceiver funcTIon. In the transceiver mode, datapresent at the high impedance port may be stored in either the A orB register or both.The select (SAB, SBA) pins determine whether data is stored ortransferred through the device in real–time. The DIR determineswhich bus will receive data when the OE is active low. In theisolation mode (OE = high), data from bus A may be stored in the Bregister and/or data from bus B may be stored in the A register.When an output function is disabled, the input function is stillenabled and may be used to store and transmit data. Only one ofthe two buses, A or B may be driven at a time.
