资 源 简 介
The SN75LVDS82 FlatLink™ receiver contains four serial-in, 7-bit parallel-out shift registers, a 7× clock synthesizer, and five low-voltage differenTIal signaling (LVDS) line receivers in a single integrated circuit.
These funcTIons allow receipt of synchronous data from a compaTIble transmitter, such as the SN75LVDS81, over five balanced-pair conductors, and expansion to 28 bits of single-ended low-voltage TTL (LVTTL) synchronous data at a lower transfer rate. The SN75LVDS82 can also be used with the SN75LVDS84 or SN75LVDS85 for 21-bit transfers.
When receiving, the high-speed LVDS data is received and loaded into registers at the rate of seven TImes (7×) the LVDS input clock (CLKIN). The data is then unloaded to a 28-bit-wide LVTTL parallel bus at the CLKIN rate.
