资 源 简 介
The 100MHz SDRAM was designed to improvememory bandwidth. It synchronizes the internaloperation of the DRAM to a system clock to achievehigher memory bandwidth per pin by pipelining internaloperations. It includes multiple independentmemory banks to allow the user to hide access andprecharge latency, provided that the system canping-pong between the banks when a new row isopened or closed. This device improves noiseimmunity to input receivers by essentially ignoringthe input pins completely, except during a narrowsetup and hold window around the rising edge of thesystem clock. The device includes a mode registerto allow the user to optimize the pipeline length ofthe device in order to minimize the read to outputdelay based on the users operating clock frequency.A self refresh mode which was normally offered onmore expensive low power EDO devices, is providedas standard equipment.
