资 源 简 介
The TPS3836, TPS3837, and TPS3838 families of supervisory circuits provide circuit iniTIalizaTIon and TIming supervision, primarily for DSP and processor-based systems.
During power-on, RESET is asserted when the supply voltage VDD becomes higher than 1.1 V. Thereafter, the supervisory circuit monitors VDD and keeps the RESET output acTIve as long as VDD remains below the threshold voltage of VIT. An internal timer delays the return of the output to the inactive state (high) to ensure proper system reset. The delay time starts after VDD has risen above the threshold voltage VIT.
When CT is connected to GND, a fixed delay time of typical 10 ms is asserted. When connected to VDD, the delay time is typically 200 ms. When the supply voltage drops below the threshold voltage VIT, the output becomes active (low) again.
