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640主板的2048位可编程LDPC码解码芯片

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  • 标      签: LDPC 芯片

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WITH sustained growth in demands for mulTImedia,wireless, and broadband services, significant effort hasbeen made to apply iteraTIve forward error correcTIon (FEC)coding techniques to advanced communicaTIons systems. Thesetechniques have proved to be very effective in extending thelimits and services of wireless communications, expanding theareal density of magnetic recording systems, and improvingthe throughput of terrestrial optical systems. Low-densityparity-check (LDPC) codes [1] have emerged as one of the topcontenders for such applications after their main rivals, turbocodes [2], have seen limited acceptance (particularly in opticalapplications) due to their high implementation complexity,decoding latency, as well as performance degradation for relativelyshort block-length and error-floors at high signal-to-noiseratios (SNRs). Research has shown that LDPC codes canachieve record-breaking performance for low SNR applications[3], [4], and are more amenable to rigorous analysis and design.They offer more flexibility in the choice of code parameters,and their decoders require simpler processing. These characteristicshave made it possible to design appropriate LDPC codesfor many communications scenarios; they have been adoptedin next generation digital video broadcasting (DVB-S2) viasatellite [5], and considered for adoption in wireless localarea network (WLAN) air interface (802.11) [6], wireless personalarea networks (WPANs) (802.12) [7], mobile broadbandwireless access (MBWA) networks (802.20) [8], advancedmagnetic and magneto-optic storage/recording systems [9], andlong-haul optical communication systems [10].
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