资 源 简 介
This project contains two folders: sim - Simulation models for the project syn - Synthesis models for the project
A Xilinx ISE 9.2i project has been setup in the syn directory, whichalready contains both the simulation and synthesis files that have beenprovided.
You are required to complete the decoder.vhd according to the memorymap guidelines given out during lectures. Once the decoder is syntactically correct, you can run a simulation in questa using thetestbench provided.
The simulation testbench provides basic checks to ensure correctread/write operations to memory and IO devices and should run tocompletion given a fully operational decoder implementation.
Once the decoder is complete, you should add a ucf file to the projectand synthesise it to create a jedec file suitable for download to theCPLD on the project boards.
