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The GAL16V8, at 3.5 ns maximum propagaTIon delay TIme, combinesa high performance CMOS process with Electrically Erasable(E2) floaTIng gate technology to provide the highest speedperformance available in the PLD market. High speed erase TImes(<100ms) allow the devices to be reprogrammed quickly and efficiently.The generic architecture provides maximum design flexibility byallowing the Output Logic Macrocell (OLMC) to be configured bythe user. An important subset of the many architecture configurationspossible with the GAL16V8 are the PAL architectures listedin the table of the macrocell description section. GAL16V8 devicesare capable of emulating any of these PAL architectures with fullfunction/fuse map/parametric compatibility.Unique test circuitry and reprogrammable cells allow complete AC,DC, and functional testing during manufacture. As a result, LatticeSemiconductor delivers 100% field programmability and functionalityof all GAL products. In addition, 100 erase/write cycles anddata retention in excess of 20 years are specified.
