资 源 简 介
VHDL Library of Arithmetic Units fdl
A comprehensive library of arithmetic units written in synthesizable VHDL code has beendeveloped. The library contains components for a variety of arithmetic operations and fordifferent speed requirements. The library components are implemented as circuit generatorsin parameterized structural VHDL code. Their modular and well-documented source codeallows for simple usage and easy customization. Highly efficient circuit architectures areused, which are optimized for synthesis and cell-based design. In particular, the implementedadder architectures are more flexible and have better performance than the ones typically usedin commercial products. This public domain VHDL library is platform independent, and itprovides circuits with comparable performance, but higher flexibility and a larger diversityof arithmetic operations compared to commercial data path libraries.
