资 源 简 介
The SN74LVC2G125 is a dual bus buffer gate, designed for 1.65-V to 5.5-V VCC operaTIon. This device features dual line drivers with 3-state outputs. The outputs are disabled when the associated output-enable (OE) input is high.
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To ensure the high-impedance state during power up or power down, OE should be TIed to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
This device is fully specified for parTIal-power-down applicaTIons using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
