资 源 简 介
Preface xiiiForeword xvAcknowledgments xixChapter 1: Libraries 11.1 Standard Cells 21.2 Transistor Sizing 121.3 Input-Output Pads 161.4 Library Characterization 251.5 Summary 34Chapter 2: Floorplanning 372.1 Technology File 382.2 Circuit Description 402.3 Design Constraints 452.4 Design Planning 472.5 Pad Placement 512.6 Power Planning 542.7 Macro Placement 582.8 Clock Planning 642.9 Summary 66Chapter 3: Placement 713.1 Global Placement 723.2 Detail Placement 813.3 Clock Tree Synthesis 893.4 Power Analysis 993.5 Summary 102Chapter 4: Routing 1054.1 Special Routing 1064.2 Global Routing 1084.3 Detail Routing 1154.4 Extraction 1234.5 Summary 141Chapter 5: Verification 1455.1 Functional Verification 1465.2 Timing Verification 1495.3 Physical Verification 1715.4 Summary 175Chapter 6: Testing 1796.1 Functional Test 1816.2 Scan Test 1856.3 Boundary Scan Test 1886.4 Fault Detection 1906.5 Parametric Test 1926.6 Current and Very Low-level Voltage Test 1946.7 Wafer Acceptance Test 1966.8 Memory Test 199x Contents xi6.9 Parallel Module Test 2026.10 Summary 201Index 205
