资 源 简 介
This 8-bit parallel-out serial shift register features AND-gated serial (A and B) inputs and an asynchronous clear (CLR) input. The gated serial inputs permit control over incoming data because a low at either input inhibits entry of the new data and resets the first flip-flop to the low level at the next clock pulse. A high-level input enables the other input, which determines the state of the first flip-flop. Data at the serial inputs can be changed while the clock is high or low, provided that the minimum setup-TIme requirements are met. Clocking occurs on the low-to-high-level transiTIon of the clock (CLK) input. All inputs are diode clamped to minimize transmission-line effects.
The SN74ALS164A is characterized for operaTIon from 0°C to 70°C.
