资 源 简 介
These 8-bit universal shift/storage registers feature mulTIplexed I/O ports to achieve full 8-bit data handling in a single 20-pin package. Two funcTIon-select (S0, S1) inputs and two output-enable (OE1, OE2) inputs can be used to choose the modes of operaTIon listed in the funcTIon table.
Synchronous parallel loading is accomplished by taking both S0 and S1 high. This places the 3-state outputs in the high-impedance state and permits data applied on the I/O ports to be clocked into the register. Reading out of the register can be accomplished while the outputs are enabled in any mode. Clearing occurs asynchronously when the clear (CLR) input is low. Taking either OE1 or OE2 high disables the outputs, but has no effect on clearing, shifting, or storing data.
