资 源 简 介
File/Directory Description=============================================doc DDR SDRAM reference design documentationmodel Contains the vhdl SDRAM model
oute Contains the Quartus 2000.05 project files a routed controller designsimulation Contains the vhdl testbench, modelsim project file, and librarysource Contains the vhdl source files for the DDR SDRAM reference designsynthesissynplicity Contains all synplicity project files associated with synthesizing the reference design
