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Capitalizing on two-bit-per-cell technology, IntelÒStrataFlash™ memory devices provide 2X the bits in1X the space. Other benefits include more density inless space, lowest cost-per-bit NOR devices, supportfor code and data storage, and Common Flash Interface(CFI) for easy migration to future devices.
1.0 INTRODUCTION............................................. 52.0 HARDWARE INTERFACE.............................. 52.1 Intel® StrataFlash™ Memory InterfaceSignals........................................................ 52.2 SA-1100 Processor Interface Signals .......... 52.3 Voltage Considerations................................ 63.0 SA-1100 MEMORY CONTROLLERINITIALIZATION ............................................ 73.1 Static Memory Control Registers (MSC1-0) . 73.2 Read/Write Timings ..................................... 73.3 Reset........................................................... 94.0 SUMMARY.................................................... 10FIGURESFigure 1. 28F640J5/SA-1100 Interface ............. 6Figure 2. 28F640J5 and SA-1100 at 190 MHzRead Timing Diagram ........................ 8Figure 3. 28F640J5 and SA-1100 at 190 MHzWrite Timing Diagram......................... 8TABLESTable 1. SA-1100 Memory Control RegisterTable...................................................7Table 2. Write Timing Table.............................. 9Table 3. Reset Timing Table........................... 10
