资 源 简 介
These bidirecTIonal shift registers are designed to incorporate virtually all of the features a system designer may want in a shift register. The circuit contains 46 equivalent gates and features parallel inputs, parallel outputs, right-shift and left-shift serial inputs, operaTIng-mode-control inputs, and a direct overriding clear line. The register has four disTInct modes of operaTIon, namely:
Inhibit clock (do nothing)
Shift right (in the direction QA toward QD)
Shift left (in the direction QD toward QA)
Parallel (broadside) load
Synchronous parallel loading is accomplished by applying the four bits of data and taking both mode control inputs, S0 and S1, high. The data are loaded into the associated flip-flops and appear at the outputs after the positive transition of the clock input.
