资 源 简 介
The HS-3282 is a high performance CMOS bus interfacecircuit that is intended to meet the requirements of ARINCSpecificaTIon 429, and similar encoded, TIme mulTIplexedserial data protocols. This device is intended to be used withthe HS-3182, a monolithic Dl bipolar differenTIal line driverdesigned to meet the specifications of ARINC 429. TheARINC 429 bus interface circuit consists of two (2) receiversand a transmitter operating independently as shown inFigure 1. The two receivers operate at a frequency that isten (10) times the receiver data rate, which can be the sameor different from the transmitter data rate. Although the tworeceivers operate at the same frequency, they arefunctionally independent and each receives serial data asynchronously.The transmitter section of the ARINC businterface circuit consists mainly of a First-In First-Out (FIFO)memory and timing circuit. The FIFO memory is used to holdup to eight (8) ARINC data words for transmission serially.The timing circuit is used to correctly separate each ARINCword as required by ARINC Specification 429. Even thoughARINC Specification 429 specifies a 32-bit word, includingparity, the HS-3282 can be programmed to also operate witha word length of 25 bits. The incoming receiver data wordparity is checked, and a parity status is stored in the receiverlatch and output on Pin BD08 during the 1st word. [A logic“0” indicates that an odd number of logic “1” s were receivedand stored; a logic “1” indicates that an even number of logic“1”s were received and stored]. In the transmitter the paritygenerator will generate either odd or even parity dependingupon the status of PARCK control signal. A logic “0” onBD12 will cause odd parity to be used in the output datastream.
