资 源 简 介
This octal buffer and line driver is designed specifically to improve both the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters. Taken together with the SN64BCT240 and SN64BCT241, these devices provide the choice of selected combinaTIons of inverTIng and noninverTIng outputs, symmetrical acTIve-low output-enable () inputs, and complementary OE and inputs.
The SN64BCT244 is organized as two 4-bit buffers/line drivers with separate output-enable () inputs. When is low, the device passes data from the A inputs to the Y outputs. When is high, the outputs are in the high-impedance state.
The outputs are in a high-impedance state during power up and power down while the supply voltage is less than approximately 3 V.
