资 源 简 介
CD4724B 8-bit addressable latch is a serial-input, parallel-output storage register that can perform a variety of funcTIons.
Data are inputted to a parTIcular bit in the latch when that bit is addressed (by means of input A0, A1, A2) and when WRITE DISABLE is at a low level. When WRITE DISABLE is high, data entry is inhibited; however, all 8 outputs can be conTInuously read independent of WRITE DISABLE and address inputs.
A master RESET input is available, which resets all bits to a logic "0" level when RESET and WRITE DISABLE are at a high level. When RESET is at a high level, and WRITE RESET is at a low level, the latch acts as a 1-of-8 demulTIplexer; the bit that is addressed has an active output which follows the data input, while all unaddressed bits are held to a logic "0" level.
