资 源 简 介
This Cypress series of network circuits is produced usingadvanced 0.35-micron CMOS technology, achieving theindustry’s fastest logic.The Cypress CY2DL818 fanout buffer features a single LVDSor a single-ended LVTTL-compaTIble input and eight LVDSoutput pairs.Designed for data communicaTIons clock management applicaTIons,the large fanout from a single input reduces loadingon the input clock. The Cypress CY2DL818 is ideal for bothlevel translaTIons from single-ended to LVDS and/or for thedistribution of LVDS-based clock signals.The Cypress CY2DL818 has configurable input and outputfunctions. The input can be selectable for LVCMOS/LVTTL,LVPECL, or LVDS signals, while the output drivers supportstandard and high-drive LVDS. Drive either a 50-ohm or100-ohm line with a single part number/device.
Features• Low voltage operation• VDD = 3.3V• 1:8 fanout• Single-input-configurable for LVDS, LVPECL, or LVTTL• 8 pair of LVDS Outputs• Drives either a 50-ohm or 100-ohm load (selectable)• Low input capacitance• Low output skew• Low propagation delay• Typical (tpd < 4 ns)• Packages available include: TSSOP• Does not exceed Bellcore 802.3 standards• Operation at => 350 MHz – 700 Mbps
