资 源 简 介
CADENCE SIP RF ARCHITECTWhile system-in-package (SiP) design makes it possible to combine RF and analogcontent on the same substrate, it presents a number of challenges. These includedesigning and integraTIng RF/analog chips with substrate-level buried RF passivedevices as well as enabling top-level pre- and post-layout circuit simulaTIon of theenTIre SiP design. CadenceSiP RF Architect provides the proven path betweenanalog design and simulaTIon and SiP RF layout. It enables designers to create asingle, system-level, circuit simulation-ready schematic for RF/analog die, SiPsubstrate, and packaged and embedded discretes.
