资 源 简 介
These 8-bit shift registers feature gated serial inputs andan asynchronous clear. A low logic level at either inputinhibits entry of the new data, and resets the first flip-flop tothe low level at the next clock pulse, thus providing com-plete control over incoming data. A high logic level oneither input enables the other input, which will then deter-mine the state of the first flip-flop. Data at the serial inputsmay be changed while the clock is HIGH or LOW, but onlyinformaTIon meeTIng the setup and hold TIme requirementswill be entered. Clocking occurs on the LOW-to-HIGH leveltransiTIon of the clock input. All inputs are diode-clamped tominimize transmission-line effects.n Gated (enable/disable) serial inputsn Fully buffered clock and serial inputsn Asynchronous clearn Typical clock frequency 36 MHzn Typical power dissipation 80 mW
