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SN54AHC273, SN74AHC273,pdf(OCT

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  • 标      签: Flip-Flops

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These circuits are posiTIve-edge-triggered D-type flip-flops with a direct clear (CLR) input. InformaTIon at the data (D) inputs meeTIng the setup TIme requirements is transferred to the Q outputs on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse. When CLK is at either the high or low level, the D input has no effect at the output.
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