资 源 简 介
The TPD4S1394 provides robust system level ESD soluTIon for the IEEE.1394 port along with a live inserTIon detecTIon mechanism for high-speed lines interfacing a low-voltage, ESD sensiTIve core chipset. This device protects and monitors up to two differential input pairs. The optimized line capacitance allows to protect the data lines with data rate in excess of 1.6 GHz without degrading signal integrity.
The TPD4S1394 incorporates a live insertion circuit whose output state changes when improper voltage levels are present on the input data lines. The FWPWR_EN signal controls an external FireWire port power switch. During the live insertion event if there is a floating GND or a high level signal at the D+, D– pins, the internal comparator will detect the changes and pull the FWPWR_EN signal to low state.
