资 源 简 介
This application note describes the output timing parameters for Altera®devices, explains how Altera defines tCO results, and presents techniquesfor calculating the output timing for your system. In addition, a sampleDDR2 interface link is presented and analyzed for calculating outputtiming.Detailed timing information is available in the device handbooks andfrom the Quartus® II software. The timing information in the handbookspresumes a sample design and is specific to that one implementation forthat device. Your implementation may be different, so you should obtaintiming data that directly applies to your system by using the valuesreported by the Quartus II timing analyzer (TAN) or TimeQuest.When dealing with output timing parameters such as tCO, the Quartus IIsoftware is only aware of the FPGA-related timing components. TheQuartus II software does not have information on the PCB or thereceiving device. It is important to understand exactly what the tCO resultparameters represent and to understand how to use the timing reportedby the Quartus II software to determine complete system timing.
