资 源 简 介
Xilinx CoolRunner XPLA3 CPLDs provide designers with several useful configuration optionsfor each macrocell. These options allow greater flexibility when creating complex designs.Some of the configurations available are: data register (D, T, and Latch), input register, buriedcombinatorial or registered node, and I/O port. Combinations of these configurations can beused to increase macrocell utilization.In addition to better macrocell utilization, the XPLA3 input registers have a very short setuptime. This feature is beneficial when data transfers between devices on a board must occurwithin one clock cycle.
