资 源 简 介
This bus-interface register is designed to eliminate the extra packages required to buffer exisTIng registers and provide extra data width for wider address/data paths or buses carrying parity. The CY74FCT821T is a 10-bit-wide buffered version of the popular CY74FCT374 funcTIon. This device is ideal for use as an output port requiring high IOL/IOH.
This device is designed for high-capacitance load drive capability, while providing low-capacitance bus loading at both inputs and outputs. Outputs are designed for low-capacitance bus loading in the high-impedance state.
This device is fully specified for parTIal-power-down applicaTIons using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
