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The SN54LVC373A octal transparent D-type latch is designed for 2.7-V to 3.6-V VCC operaTIon, and the SN74LVC373A octal transparent D-type latch is designed for 1.65-V to 3.6-V VCC operaTIon.
While the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the logic levels set up at the D inputs.
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pullup components.
