资 源 简 介
These octal bus transceivers are designed for asynchronous two-way communicaTIon between data buses. The control-funcTIon implementaTIon allows for maximum flexibility in TIming.
These devices allow data transmission from the A bus to the B bus or from the B bus to the A bus, depending upon the logic levels at the output-enable (OEAB and ) inputs.
The output-enable inputs disable the device so that the buses are effectively isolated. The dual-enable configuration gives the transceivers the capability to store data by simultaneously enabling OEAB and . Each output reinforces its input in this transceiver configuration. When both OEAB and are enabled and all other data sources to the two sets of bus lines are in the high-impedance state, both sets of bus lines (16 total) remain at their last states.
