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SN74HC273-Q1,pdf(Octal D-Type

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  • 上传时间:2021-06-24
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  • 标      签: Flip-Flop

资 源 简 介

This circuit is a posiTIve-edge-triggered D-type flip-flop with a direct clear (CLR) input. InformaTIon at the data (D) inputs meeTIng the setup TIme requirements is transferred to the Q outputs on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a particular voltage level and is not related directly to the transition time of the positive-going pulse. When CLK is at either the high or low level, the D input has no effect at the output.
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