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AD9240,pdf datasheet (Monolith

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The AD9240 uses a four-stage pipeline architecture with awideband input sample-and-hold amplifier (SHA) implementedon a cost-effecTIve CMOS process. Each stage of the pipeline,excluding the last, consists of a low resoluTIon flash A/D connectedto a switched capacitor DAC and interstage residueamplifier (MDAC). The residue amplifier amplifies the differencebetween the reconstructed DAC output and the flash inputfor the next stage in the pipeline. One bit of redundancy is usedin each of the stages to facilitate digital correcTIon of flash errors.The last stage simply consists of a flash A/D.
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