资 源 简 介
The DS90C383 transmitter converts 28 bits of LVCMOS/LVTTL data into four LVDS (Low Voltage DifferenTIal Signaling)data streams. A phase-locked transmit clock is transmittedin parallel with the data streams over a fifth LVDS link.Every cycle of the transmit clock 28 bits of input data aresampled and transmitted. The DS90CF384 receiver convertsthe LVDS data streams back into 28 bits of LVCMOS/LVTTL data. At a transmit clock frequency of 65 MHz, 24 bitsof RGB data and 3 bits of LCD TIming and control data(FPLINE, FPFRAME, DRDY) are transmitted at a rate of 455Mbps per LVDS data channel. Using a 65 MHz clock, thedata throughputs is 227 Mbytes/sec. The transmitter is offeredwith programmable edge data strobes for convenientinterface with a variety of graphics controllers. The transmittercan be programmed for Rising edge strobe or Fallingedge strobe through a dedicated pin. A Rising edge transmitterwill inter-operate with a Falling edge receiver(DS90CF384) without any translaTIon logic. Both devices arealso offered in a 64 ball, 0.8mm fine pitch ball grid array(FBGA) package which provides a 44 % reducTIon in PCBfootprint compared to the TSSOP package.
