A Memory Efficient Serial LDPC

Recently, a number of LDPC decoder architectures havebeen proposed [3]- [8]. These architectures have implementedthe widely used Sum Product Algorithm with various approachesto saTIsfy throughput and hardware requirements. Theneed for large hardware resources is a significant problemin the implementaTIon of an LDPC decoder. Mostly, serialarchitectures that require lesser hardware than parallel implementaTIonsare used. In [4] and [5] a memory efficient turbodecoding algorithm for LDPC codes is proposed. In [11] theissues relaTIng to the implementation of a min-sum LDPC decoderis explored. In [2] an offset min-sum algorithm offeringtradeoff between performance and complexity is explored tosave extrinsic message memory. In [1] an approximate minconstraint for check node update is proposed. The approximationis exploited by the decoder to reduce hardware for checknode computation units without any noticeable degradationin bit error rate performance. We observe that the bulk ofhardware requirement for the serial LDPC decoder lies inthe memory used for storing the extrinsic values(check tobit or bit to check) and hence attempt to reduce it. Theproposed modification to the SPA explained in section IIIis identical to the one proposed in [1] but we implementthe approximation in log-tanh domain to facilitate our serialdecoder architecture. The proposed decoder stores only fewbit to check messages which is very efficient when comparedto architectures proposed in [6], [7] which store all the bitto check messages and also check to bit messages. Whencompared to the serial decoder [2] our design storeslesser number of extrinsic values and requires lesser memoryto store intermediate partial sums. The proposed decoder isexplained in section IV.