资 源 简 介
This single bus buffer gate is designed for 1.65-V to 5.5-V VCC operaTIon.
The SN74LVC1G126 is a single line driver with a 3-state output. The output is disabled when the output-enable (OE) input is low.
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To ensure the high-impedance state during power up or power down, OE should be TIed to GND through a pulldown resistor; the minimum value of the resistor is determined by the current-sourcing capability of the driver.
This device is fully specified for parTIal-power-down applicaTIons using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
