资 源 简 介
These monolithic, fully synchronous, programmable counters uTIlize Series 54/74 TTL circuitry to achieve 32-megahertz typical maximum operaTIng frequencies. These six-bit serial binary counters feature buffered clock, clear, and enable inputs to control the operaTIon of the counter, and a strobe input to enable or inhibit the rate input/decoding AND-OR-INVERT gates. The outputs have addiTIonal gating for cascading and transferring unity-count rates.
The counter is enabled when the clear, strobe, and enable inputs are low. With the counter enabled, the output frequency is equal to the input frequency multiplied by the rate input M and divided by 64, ie.:
When the rate input is binary 0 (all rate inputs low), Z remains high.
