首页| 行业标准| 论文文档| 电子资料| 图纸模型
购买积分 购买会员 激活码充值

您现在的位置是:团子下载站 > VHDL/FPGA/Verilog > it is a verilog code written for FIFO in modelsim simulator and it will synthesize in xinlix ise 8

it is a verilog code written for FIFO in modelsim simulator and it will synthesize in xinlix ise 8

  • 资源大小:32 K
  • 上传时间:2021-04-08
  • 下载次数:0次
  • 浏览次数:65次
  • 资源积分:1积分
  • 标      签: synthesize simulator modelsim verilog

资 源 简 介

it is a verilog code written for FIFO in modelsim simulator and it will synthesize in xinlix ise 8.2i.i have tested it om my kit.[i mae my own kit for spartan2 device].you can use this code in any DSP project in which data entry is required.
VIP VIP