资 源 简 介
The Intersil HCTS160MS is a RadiaTIon Hardened high speedpresettable BCD decade synchronous counter that features anasynchronous reset and look-ahead carry logic. CounTIng andparallel presetTIng are accomplished synchronously with the lowto-high transiTIon of the clock. A low level on the synchronousparallel enable input, SPE, disables counting and allows data atthe preset inputs, P0 - P3, to be loaded into the counter. Thecounter is reset by a low on the master reset input, MR. Two countenables, PE and TE are provided for n-bit cascading. TE alsocontrols the terminal count output, TC. The terminal count outputindicates a maximum count for one clock pulse and is used toenable the next cascaded stage to count.
