资 源 简 介
The SN74ALS568A decade counter and ´ALS569A binary counters are programmable, count up or down, and offer both synchronous and asynchronous clearing. All synchronous funcTIons are executed on the posiTIve-going edge of the clock (CLK) input.
The clear funcTIon is iniTIated by applying a low level to either asynchronous clear (ACLR) or synchronous clear (SCLR). Asynchronous (direct) clearing overrides all other functions of the device, while synchronous clearing overrides only the other synchronous functions. Data is loaded from the A, B, C, and D inputs by holding load () low during a positive-going clock transition. The counting function is enabled only when enable P (ENP) and enable T (ENT) are low and ACLR, SCLR, and are high.
